Low voltage transient voltage suppressor and method of making

ABSTRACT

A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device ( 72 ) provides an enhanced gain operation, while device ( 88 ) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

[0001] The present application is based on prior U.S. application No.09/849,720, filed on May 4, 2001, which is hereby incorporated byreference, and priority thereto for common subject matter is herebyclaimed.

BACKGROUND OF THE INVENTION

[0002] The present invention relates in general to Transient VoltageSuppression (TVS) devices and, more particularly, to low voltage TVSdevices.

[0003] Virtually all electronic devices are susceptible to transientperturbations such as electrostatic discharge or electromagneticallycoupled interference. The perturbations most often occur at theInput/Output (I/O) interfaces to the electronic devices. Typicalexamples of I/O interfaces susceptible to the transient perturbations,or signals, are power supply input terminals and data bus terminals toname only a few.

[0004] Zener or avalanche diodes, to be referred to as TVS junctiondiodes, have typically been used to protect the electronic devices fromdamage caused by the transient voltage signals. TVS junction diodesplaced into electronic devices for transient suppression are reversebiased under normal, non-transient conditions. During transientconditions, however, the reverse bias voltage exceeds the reversebreakdown voltage and the TVS junction diode clamps the transientvoltage to be equal to the reverse breakdown voltage of the diode,thereby preventing the transient voltage from exceeding the maximumvoltage that can be sustained by the electronic device.

[0005] Prior art TVS junction diodes perform well for high voltage (>5volt) applications, but pose specific detrimental characteristics in lowvoltage (<5 volt) applications. The detrimental characteristics of lowvoltage TVS junction diodes include high leakage current and highcapacitance. Battery operated electronic devices using TVS junctiondiodes for transient voltage protection are particularly vulnerable toleakage current caused by the TVS junction diode, since the batteryprovides limited current capability. TVS junction diodes operating inthe low (<5V) voltage range typically demonstrate leakage current in themilliamp (mA) range.

[0006] Electronic devices today are designed to operate at batterysupplied potentials below 5 volts, such as 3 volts and 1.8 volts or evenlower. The current requirements of the battery operated circuits arebeing driven lower as well. TVS junction diode protection devices are nolonger acceptable in the lower voltage ranges due to the excessiveleakage current properties below 5 volts. Prior art TVS devices, such asa punch-through, 3-layer devices, while achieving low voltage protectionat low leakage current, exhibit several undesirable characteristics,such as negative resistance, or snapback, and lack of punch-throughvoltage control. Consequently, the punch-through voltage obtained fromdevice to device is randomly distributed.

[0007] Hence, there is a need for a TVS device capable of operation inthe sub-5 volt range, with no snapback, acceptable leakage current andlow capacitance, having tight control over the clamping voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is an application diagram illustrating a TVS device;

[0009]FIG. 2 is a diagram illustrating a Metal Oxide Semiconductor (MOS)device used as a low voltage, TVS device;

[0010]FIG. 3 is a schematic diagram illustrating the equivalent circuitof the voltage suppression device of FIG. 2;

[0011]FIG. 4 is a threshold curve useful in explaining the operation ofthe TVS device of FIG. 2;

[0012]FIG. 5 is a diagram illustrating a MOS device used as asymmetrical, clipping TVS device;

[0013]FIG. 6 is a schematic diagram illustrating the equivalent circuitof the symmetrical, clipping TVS device of FIG. 5;

[0014]FIG. 7 is a threshold curve useful in explaining the operation ofthe symmetrical TVS device of FIG. 5;

[0015]FIG. 8 illustrates a MOS device with an integral gate-drainconnection used as a TVS device;

[0016]FIG. 9 illustrates an alternate MOS device with an integralgate-drain connection used as a TVS device;

[0017]FIG. 10 illustrates a trench MOS device used as a TVS device;

[0018]FIG. 11 illustrates a modified trench MOS device with topsidedrain contact;

[0019]FIG. 12 illustrates an alternate trench device used as a TVSdevice; and

[0020]FIG. 13 illustrates a lateral MOS device used as a TVS device;

[0021]FIG. 14 is a schematic diagram of an integrated circuit includingan insulated gate bipolar transistor (IGBT)-based TVS device;

[0022]FIG. 15 is a cross-sectional view of the IGBT-based TVS device;

[0023]FIG. 16 is a cross-sectional view of the IGBT-based TVS device inan alternate embodiment; and

[0024]FIG. 17 is a cross-sectional view of an IGBT-based TVS device withan alternate gate biasing arrangement; and

[0025]FIG. 18 is a cross-sectional view of the TVS device in a planarembodiment.

DETAILED DESCRIPTION OF THE DRAWINGS

[0026] In FIG.1, an application of TVS device 4 is illustrated wherebyTVS device 4 isolates utilization circuit 2 from voltage transientspresent on power supply terminals V_(cc) and V_(dd). TVS device 4 iseffective to suppress both negative and positive transient potentialsacross utilization circuit 2. It should be noted, that various otherapplications exist for TVS device 4, such as a protection device usedfor I/O data lines and various other interfaces. Block 6 may denote anintegrated circuit, for example, whereby utilization circuit 2 and TVSdevice 4 coexist on the same die. Conversely, block 6 may denote aprinted circuit board, for example, whereby TVS device 4 is a discretecomponent providing protection to utilization circuit 2.

[0027] Turning to FIG. 2, a vertical MOS device 10 is illustrated,having source terminals 12 and 14, gate terminal 20 and drain terminal34. Drain terminal 34 is the header of the package encapsulating TVSdevice 10. Regions 18 and 22 are N⁺ doped regions and regions 16 and 24are P⁺ doped regions. Regions 26 and 28 form P⁻ doped well regions.Region 30 is a N⁻ drift region and region 32 is a N⁺ region. Anadvantage of the structure of TVS device 10 is the gate to drainconnection 36. Connection 36 provides that the drain voltage V_(d) andthe gate voltage V_(g) are equivalent and is typically connected to theI/O pin requiring protection, such as a supply terminal or a dataterminal. It should be noted that the device illustrated in FIG. 2 isvery similar to an Insulated Gate Bipolar Transistor (IGBT), where thedrain terminal is replaced by a collector terminal of the IGBT andregion 32 is doped P⁺ instead of N⁺. Connection 36 can be an externalconnection used for discrete MOS or IGBT packages or can be integratedinto the device during the manufacturing stage of the device.

[0028] Turning to FIG. 3, an equivalent circuit 38 of the TVS device ofFIG. 2 is illustrated. N-type MOS (NMOS) device 40 is shown to beconnected in parallel with diode 42, such that the drain terminal oftransistor 40 is coupled to the gate terminal of transistor 40 and thecathode terminal of diode 42. The anode of diode 42 is coupled to thesource terminal of transistor 40 at ground potential, for example. Diode42 is an intrinsic diode created within MOS device 40 by the P-Ninterface between regions 28 and 30 and between regions 26 and 30.Terminals 50 and 52 are considered to be the cathode and anodeconnections, respectively, of TVS device 38. Using terminals 50 and 52as the cathode and anode conductors of a two-terminal TVS device, TVSdevice 38 is used as a drop in replacement for most TVS junction diodeapplications.

[0029] The anode of diode 42 is coupled to ground potential, forexample, at the source terminal of transistor 40. A negative potential,exceeding the barrier potential of diode 42, applied at the drainterminal of transistor 40 and the cathode terminal of diode 42, causesdiode 42 to become forward biased. FIG. 4 illustrates conductive region44 of intrinsic diode 42. Once the potential across diode 42 hasexceeded the barrier potential of diode 42, negative drain to sourcecurrent is conducted by diode 42, substantially limiting the potentialdrop across diode 42 to the barrier potential. As the negative drain tosource current increases through diode 42, however, the voltage dropacross diode 42 increases slightly as shown in region 44.

[0030] Region 46 of FIG. 4 denotes a region where NMOS transistor 40 anddiode 42 are substantially non-conductive. As the gate to sourcevoltage, V_(gs), of NMOS transistor 40 increases toward the thresholdvoltage, V_(thresh), a small amount of current conducts from the drainterminal of transistor 40 to the source terminal of transistor 40. Thesmall amount of current conducted by TVS device 38 in region 46 is knownas the sub-threshold leakage current. Minimization of the amount ofleakage current conducted in region 46 is desired to reduce powerconsumption of TVS device 38. The amount of leakage current conducted byeither MOS or IGBT based TVS device 38 is typically in the nanoamp (nA)range, while the amount of leakage current conducted by a sub-5V TVSjunction diode is typically in the milliamp (mA) range. The substantialdecrease in the amount of power consumed by TVS device 38, therefore, isa distinct advantage over the use of standard, TVS junction diode basedtransient voltage suppressors.

[0031] Region 48 of FIG. 4 defines the forward conductive region of TVSdevice 38. Once the voltage at the gate and drain terminals oftransistor 40 exceeds the threshold voltage of transistor 40, transistor40 becomes conductive, substantially maintaining a constant gate tosource voltage, or clamp voltage. Since the threshold voltage of the MOSor IGBT based TVS device is readily varied between approximately 0.5volts and 5.0 volts using implantation adjustments, the clamp voltage iseasily adjusted. MOS or IGBT based TVS devices provide operation in thesub-5 volt region with low leakage current capability. The slope of thecurve in region 48 is increased to near vertical through increasing thegain of the MOS or IGBT device.

[0032] A further advantage of using MOS or IGBT based TVS devicesinclude protection of the gate oxide from voltage transients through theuse of the intrinsic diode 42. As can be seen in FIG. 4, region 44 is alimitation of the negative excursion of the gate to source voltage bybody diode 42. Body diode 42 also protects the gate oxide from rupturewith positive gate-source over-voltages, depending on the breakdownvoltage of diode 42. Another advantage exhibited by the MOS or IGBTbased TVS device is the low series resistance and low capacitance, whichis controlled by the doping of region 30. A further advantage is thegain control of TVS device 38, through the proper selection of thethickness of gate oxide layer 54 and the channel packing density.

[0033]FIG. 5 illustrates a vertical MOS clipping device 11 havingmultiple gate electrodes 25 interconnected using conductor 27 and havinga common connection to drain 9. Source electrodes 21 and 23 provide theexternal connections to TVS device 11. Source regions 19 are N⁺ dopedand are formed inside P-well regions 15. Region 13 is an N doped region.

[0034] Turning to FIG. 6, an equivalent circuit 41 of the TVS device ofFIG. 5 is illustrated. N-type MOS (NMOS) device 29 is shown to beconnected in parallel with diode 31, such that the drain terminal oftransistor 29 is coupled to the gate terminal of transistor 29 and thecathode terminal of diode 31. The anode of diode 31 is coupled to thesource terminal of transistor 29. Additionally, NMOS device 35 is shownto be connected in parallel with diode 33, such that the drain terminalof transistor 35 is coupled to the gate terminal of transistor 35 andthe cathode terminal of diode 33. The anode of diode 33 is coupled tothe source terminal of transistor 35. Diodes 31 and 33 are intrinsicdiodes created within MOS devices 29 and 35 by the P-N interface betweenregions 15 and 13. Terminals 21 and 23 are the external connections ofTVS device 11. The gate terminals of transistors 29 and 35 are coupledtogether at the cathode terminals of diodes 31 and 33.

[0035]FIG. 7, in combination with FIG. 6, illustrates the operation ofTVS device 41. A positive voltage, V₃₇, is applied at terminal 37 withrespect to terminal 39. Diode 31 is forward biased and places apotential, V₅₁, at node 51, where V₅₁ is defined by the followingequation, V₅₁=V₃₇−V₃₁, where V₃₁ is the barrier potential of diode 31.When V₅₁ increases above the threshold voltage of transistor 35,transistor 35 becomes conductive and creates a current path fromterminal 37, through diode 31, through transistor 35 to terminal 39.Transistor 29 remains non-conductive, since the source voltage oftransistor 29 exceeds the gate voltage of transistor 29. The voltage atterminal 37, therefore, is clamped to the threshold voltage oftransistor 35 added to the barrier potential of diode 31, indicated asV⁺in FIG. 7. Conversely, a positive voltage, V₃₉, is applied at terminal39 with respect to terminal 37. Diode 33 is forward biased and places apotential, V₅₁, at node 51, where V₅₁ is defined by the followingequation, V₅₁=V₃₉−V₃₃, where V₃₃ is the barrier potential of diode 33.When V₅₁ increases above the threshold voltage of transistor 29,transistor 29 becomes conductive and creates a current path fromterminal 39, through diode 33, through transistor 29 to terminal 37.Transistor 35 remains non-conductive, since the source voltage oftransistor 35 exceeds the gate voltage of transistor 35. The voltage atterminal 39, therefore, is clamped to the threshold voltage oftransistor 29 added to the barrier potential of diode 33, indicated asV⁻ in FIG. 7. Regions 45 and 47 denote regions where NMOS transistor 29,diode 31, NMOS transistor 35 and diode 33 are substantiallynon-conductive. The TVS device of FIG. 6, therefore, provides a circuitwhich suppresses both positive and negative excursions of transientpotentials applied across terminals 37 and 39 in a symmetrical manner.

[0036]FIG. 8 illustrates an alternate TVS device utilizing a split gateMOS structure and an integral gate-drain connection. The device of FIG.8 demonstrates the capability of providing on-chip gate to drainconnections, obviating the need for a connection strap between the gateto drain terminal as shown in FIG. 2. Split gate terminals 56 and 58overlap source regions 18 and 22. Metal layer 64 provides contact togate terminals 56 and 58, while insulating layers 68 and 66 provide therequired electrical isolation between gate and source terminals. N⁺region 51 provides the integrated contact to N⁻ drift region 53 tocomplete the gate to drain connection.

[0037]FIG. 9 illustrates an alternate TVS device using gate feed 57 andmetal strap 65 to provide an electrical contact to N⁺ region 61. Scribegrid 63 is an N doped region making contact with N⁺ substrate 32 tocomplete the gate to drain connection.

[0038]FIG. 10 illustrates a trench TVS device 72 having trench gate 88providing a built in connection to N- drift region 86, which forms thedrain region. Trench gate 88 is formed using polysilicon. N⁺ sourceregions 80 and 82 are in electrical contact to source metal layer 74.Oxide layer 76 is formed, which provides the proper isolation betweenpolysilicon gate 88 and source regions 80 and 82. An anisotropic spaceretch is used to provide the built in connection between gate 88 anddrain region 86. N⁺ drain contact region 75 provides the drain contactto device 72. It should be noted that TVS device 72 is easily convertedinto an IGBT device having emitter regions 80 and 82 by making draincontact region into a P+ doped collector region. Once TVS device 72becomes conductive, due to the interconnect line 241 to connect gateterminal 213 to anode 205 of diode 204 as shown.

[0039] Semiconductor substrate 220 is mounted on a die flag 232 ofsemiconductor package 210 with a die attach material that has a lowelectrical and thermal resistance. In one embodiment, die flag 232 isformed with a low resistance metal such as copper. In one embodiment,die flag 232 operates as lead 208 to provide a low resistance externalconnection to integrated circuit 200. External connections to lead 209are made with a standard wire bond or clip lead arrangement.

[0040] A bonding wire 234 connects anode 205 of diode 204 to die flag232 so that gate terminal 213 and collector region or terminal 216operate at substantially the same potential.

[0041] In operation, a positive excursion of transient signal V_(trans)is coupled through die flag 232, bonding wire 234 and interconnect line241 to gate terminal 213. If the amplitude of V_(trans) is greater thanthe conduction threshold of IGBT 202, body region 228 inverts under gateterminal 213 to form a channel 230 that allows surge current I_(trans)to flow through IGBT 202 along a current path 249 as shown. IGBT 202 isreferred to as a vertical transistor because I_(trans) flows verticallythrough the device between top surface 238 and bottom surface 236.

[0042] Surge current I_(trans) causes a junction 251 between sublayer216 and epitaxial layer 217 to forward bias, injecting minority carriersinto sublayer 216 and epitaxial layer 217. The minority carriersconductivity modulate epitaxial layer 217, so that its resistivity isreduced, which reduces the on-state resistance of IGBT 202. Becauseepitaxial layer 217 is lightly doped to provide a low junction 251capacitance, the conductivity modulation of tan result in an effectiveresistivity reduction of several orders of magnitude at high I_(trans)current levels. For region 88 is achieved externally or at the edgeterminations of TVS device 73. It should be noted that TVS device 73,having N⁺ emitter regions, is easily converted into an IGBT device byreplacing N⁺ drain region 75 by a P⁺ collector region.

[0043]FIG. 13 illustrates lateral TVS device 118 having source contacts130 and 136 and an electrical connection 132 between drain 122 and gate124. Drain and source regions, 122 and 126 respectively, are N⁺ dopedregions. Region 120 is an N⁻ doped region, forming a built-inpunchthrough diode with P⁺ substrate 134. The punchthrough is designedto occur above the threshold of TVS device 118 at between 6-10 volts,for example. The punchthrough diode provides an additional current pathfor handling high surge currents. P⁺ sinker region 128 provides atopside substrate contact.

[0044]FIG. 14 shows a schematic diagram of an integrated circuit 200including an IGBT-based TVS device 201 housed in a semiconductor package210 having a lead 208 coupled to an external bus 215 and a lead 209operating at ground potential. Bus 215 carries an information signalV_(DATA) that operates between zero and two volts, and is susceptible toa high energy, high voltage transient signal V_(TRANS) that is inducedby electrostatic discharge or a line disturbance and effectivelysuperposed on information signal V_(DATA).

[0045] TVS device 201 includes an IGBT 202 and back-to-back diodes203-204. IGBT 202 is coupled across leads 208-209 of semiconductorpackage 210 to dissipate the energy induced by V_(TRANS) by turning onwhen V_(TRANS) is greater than a predefined level. Energy is dissipatedby shunting an associated surge current I_(TRANS) when V_(TRANS) reachesthe predefined level typically set by adjusting the gate-emitterconduction threshold of IGBT 202 during fabrication by varying thedopant level that is implanted in the channel region to adjust theconduction threshold of the device.

[0046] Integrated circuit 200 may include an input transistor 212 whosesource and gate electrodes are coupled to leads 208-209, respectively,for coupling V_(DATA) to other circuitry of integrated circuit 200. Itsgate electrode is coupled to lead 208 and formed to operate at anamplitude less than its gate rupture potential which, in one embodiment,is about twenty volts. TVS device 201 protects the gate oxide oftransistor 212 from being ruptured by an excessive electric field byclamping V_(TRANS) to limit its voltage magnitude. Alternatively, TVSdevice 201 could be formed as a two-lead stand alone integrated circuitthat suppresses transient signals on external data and/or power supplylines to protect external circuitry.

[0047] IGBT 202 may be either a vertical or planar device that isconfigured to present leads 208-209 with a low capacitance. Dopinglevels are selected so that IGBT 202 has a gate-emitter conductionthreshold of about 2.3 volts and a low subthreshold collector-emitterleakage current. A gate terminal 213 is connected with an interconnectline 241 to a collector terminal and to lead 208, while an interconnectline 240 operates as an emitter terminal connected to lead 209, whichoperates at ground potential. The gate connection results in IGBT 202turning on when the voltage on lead 208 is greater than about 2.3 volts.Consequently, when lead 208 operates between zero and two volts, i.e.,within the V_(DATA) range, TVS device 201 operates as a substantiallyopen circuit, while turning on to shunt current when its gate voltageexceeds about 2.3 volts to effectively clamp lead 208 to a voltage levelless than about five volts.

[0048] Diodes 203-204 are formed on the same die as IGBT 202 andconfigured to protect the IGBT 202 gate from destructively breaking downwhen V_(TRANS) undergoes a negative transition. When V_(TRANS) isnegative, diode 203 is forward biased while diode 204 is reverse biased.Diodes 203-204 are doped to breakdown at a voltage in a range betweensix and seven volts. Depending on the gate oxide breakdown or rupturevoltage in a particular application, virtually any number ofseries-connected back-to-back diodes can be formed between the emitterand gate terminals of IGBT 202 to set the protection voltage to a valueless than the rupture voltage. For example, in an embodiment where thegate oxide rupture voltage is twenty volts, two pairs of seriallyconnected back-to-back diodes can be used to maintain the gate voltageless than twelve volts.

[0049] To see the operation of TVS device 201, assume that inputtransistor 212 has a destructive gate to source breakdown or gate oxiderupture of five volts and that IGBT 202 is doped to have a conductionthreshold V_(TH)=2.3 volts.

[0050] Since IGBT 202 has a low capacitance as well as a higherconduction threshold than the amplitude of V_(DATA), under normalconditions, TVS device 201 effectively operates as an open circuit withrespect to leads 208-209. Now assume an electrostatic discharge or othersystem event induces a five ampere transient signal V_(TRANS) on bus 215at a voltage level greater than V_(TH)=2.3 volts. TVS device 201 turnson to shunt a transient current I_(TRANS) generated by V_(TRANS),thereby dissipating the transient energy and clamping the voltage at thegate of transistor 212 to a value less than five volts. I_(TRANS) causesinternal regions of IGBT 202 to be conductivity modulated, which resultsin a low on-state resistance and low voltage drop. For example, in anembodiment in which IGBT 202 has an effective active area of about 0.7millimeters², TVS device 201 can clamp lead 208 to a voltage level ofless than about five volts while shunting five amperes of peak I_(TRANS)current. Consequently, the gate of input transistor 212 is maintainedbelow its destructive rupture value, which avoids permanent damage totransistor 212 and increases the reliability of integrated circuit 200.

[0051]FIG. 15 is a cross-sectional view of integrated circuit 200including IGBT 202 and diodes 203-204 of TVS device 201 as formed on asemiconductor substrate 220. In one embodiment, IGBT 202 is implementedas an n-channel device.

[0052] A sublayer 216 is formed at a bottom surface 236 of substrate 220and heavily doped to have a p-type conductivity to operate aslow-resistance collector terminal of IGBT 202. The heavy doping levelsalso ensure that a uniform, high quality ohmic contact can be made tobottom surface 236. In one embodiment, sublayer 216 is made ofmonocrystalline silicon.

[0053] An epitaxial layer 217 is formed over sublayer 216 to operate asa drift region of IGBT 202. Epitaxial layer 217 is lightly doped to havean n-type conductivity so that its metallurgical junction with sublayer216 has a low capacitance in order to present a minimal reactive load sothat TVS device 201 operates as substantially an open circuit when IGBT202 is turned off. In one embodiment, epitaxial layer 217 is formed to athickness of about twelve micrometers and a doping concentration ofabout 10¹⁴ atoms/centimeter

[0054] A body region 228 is formed by diffusing p-type impurities intoepitaxial layer 217 through a top surface 236 of semiconductor substrate220. In one embodiment, body region 228 has a depth of about twomicrometers. In the plane of FIG. 15, integrated circuit 200 is shown ashaving two body regions 228. However, these regions are electricallycoupled together out of the view plane so as to effectively comprise asingle body region 228.

[0055] A body contact region 224 is formed in body region 228 to providean ohmic contact at top surface 238. Accordingly, body contact region224 is heavily doped to have a p-type conductivity and is formed to adepth of, for example, 0.6 micrometers.

[0056] An emitter region 222 is formed at top surface 238 within bodyregion 228. In one embodiment, emitter region 222 is heavily doped withan n-type conductivity and a depth of about 0.15 micrometers.

[0057] A dielectric material is formed over surface 238 to provide agate dielectric 214 of IGBT 202. In one embodiment, gate dielectric 214comprises thermally grown silicon dioxide formed to a thickness of abouttwo hundred fifty angstroms.

[0058] A conductive material is deposited over surface 238 and patternedto form a gate terminal 213 of IGBT 202 over gate dielectric region 214.In one embodiment, gate terminal 213 is formed with dopedpolycrystalline silicon to function with gate dielectric 214 as a gatestructure of IGBT 202.

[0059] The conductive material is further patterned to form cathoderegions 205 and 207 and a common anode region 206 over a dielectricregion 242. Cathode regions 205 and 207 are doped to have an n-typeconductivity and common anode region 206 is doped to have a p-typeconductivity. Back to back diodes 203 and 204 result from themetallurgical junctions of common anode region 206 with cathode region205 and cathode region 207, respectively, as shown. Diodes 203-204 aredoped to break down in a range between about six and about seven voltsto prevent damage to gate dielectric 214 during a negative-goingV_(TRANS) voltage spike. Two additional series-coupled back-to-backdiodes are typically added to increase the protection voltage to a rangebetween about twelve volts and about fourteen volts.

[0060] A metal layer is deposited and patterned to form interconnectline 240 that operates as an emitter terminal. Interconnect line 240 isconnected to emitter region 222, to body contact region 224 and to anoderegion 207 of diode 203. The metal layer is further patterned to produceinterconnect line 241 to connect gate terminal 213 to anode 205 of diode204 as shown.

[0061] Semiconductor substrate 220 is mounted on a die flag 232 ofsemiconductor package 210 with a die attach material that has a lowelectrical and thermal resistance. In one embodiment, die flag 232 isformed with a low resistance metal such as copper. In one embodiment,die flag 232 operates as lead 208 to provide a low resistance externalconnection to integrated circuit 200. External connections to lead 209are made with a standard wire bond or clip lead arrangement.

[0062] A bonding wire 234 connects anode 205 of diode 204 to die flag232 so that gate terminal 213 and collector region or terminal 216operate at substantially the same potential.

[0063] In operation, a positive excursion of transient signal V_(TRANS)is coupled through die flag 232, bonding wire 234 and interconnect line241 to gate terminal 213. If the amplitude of V_(TRANS) is greater thanthe conduction threshold of IGBT 202, body region 228 inverts under gateterminal 213 to form a channel 230 that allows surge current I_(TRANS)to flow through IGBT 202 along a current path 249 as shown. IGBT 202 isreferred to as a vertical transistor because I_(TRANS) flows verticallythrough the device between top surface 238 and bottom surface 236.

[0064] Surge current I_(TRANS) causes a junction 251 between sublayer216 and epitaxial layer 217 to forward bias, injecting minority carriersinto sublayer 216 and epitaxial layer 217. The minority carriersconductivity modulate epitaxial layer 217, so that its resistivity isreduced, which reduces the on-state resistance of IGBT 202. Becauseepitaxial layer 217 is lightly doped to provide a low junction 251capacitance, the conductivity modulation of can result in an effectiveresistivity reduction of several orders of magnitude at high I_(TRANS)current levels. For example, at a peak I_(TRANS) current of one hundredamperes, the effective resistance of epitaxial layer 217 can be reducedby as much as a factor of three. As a result, IGBT 202 has a high gain,so large I_(TRANS) current levels are accommodated with only a smallincrease in potential on lead 208. In effect, I_(TRANS) is shunted toground potential to dissipate the energy stored in V_(TRANS), therebyclamping the voltage on lead 208 to a level that avoids damaging othercomponents of integrated circuit 200. For negative V_(TRANS) excursions,back-to-back diodes 203-204 break down to clamp the potential on gateterminal 213 to prevent gate rupture or other damage to gate dielectricregion 214.

[0065]FIG. 16 is a cross-sectional view of TVS device 201 in analternate embodiment. The structure and operation of this embodiment aresimilar to what is described above, except that a collection region 250is formed between portions of body region 228 as shown. Collectionregion 250 typically is formed using the same processing steps as bodyregion 228, and consequently has a p-type conductivity and similarjunction depth and doping concentration. A p-type collection contactregion 252 is formed within collection region 250 at top surface 238.Region 252 is heavily doped and typically formed during the sameprocessing steps used to form region 224 to ensure a high quality ohmiccontact to collection region 250.

[0066] Sublayer 216, epitaxial layer 217 and collection region 250operate as an emitter, base and collector, respectively, of a merged PNPbipolar transistor 253 that provides a current path 254 between leads208-209 that is parallel to current path 249 of IGBT 202. When IGBT 202turns on, surge current I_(TRANS) forward biases junction 251, causingminority carrier holes to be injected into epitaxial layer 217. Theholes are collected by collection region 250 as a V_(TRANS) componentcurrent I_(PNP) that is summed with I_(TRANS) and routed through leads208-209 to increase the transconductance gain and overall currentcapability of TVS device 201, thereby improving both performance andreliability.

[0067]FIG. 17 is a cross-sectional view of TVS device 201 in anotheralternate embodiment. The structure and operation are similar to theembodiments described above, except as follows.

[0068] A drift contact region 260 is formed in epitaxial layer 217 toprovide an ohmic contact at surface 238. In one embodiment, driftcontact region 260 is heavily doped to have an n-type conductivity usingthe same processing steps as region 222 to operate at substantially thesame potential as epitaxial region 217.

[0069] Gate terminal 213 is connected through interconnect line 241 todrift contact region 260 to bias gate terminal 213 at the same potentialas epitaxial region 217. Hence, gate terminal 213 is biased throughforward-biased junction 251, rather than by a direct connection to lead208. Consequently, in response to transient voltage V_(TRANS), thevoltage level on lead 208 is about 0.6 volts higher than what it wouldbe if gate terminal 213 were connected to lead 208 through a bondingwire. Since no bonding wire is needed to bias gate terminal 213, theFIG. 17 embodiment typically has a lower inductance and therefore afaster response and lower cost.

[0070]FIG. 18 is a cross-sectional view of TVS device 201 in anembodiment as a planar or lateral device. The operation and structureare similar to those described above except as follows.

[0071] Sublayer 216 has an n-type conductivity and typically may beheavily doped to provide a ground plane, especially if other circuitrybesides TVS device 201 is integrated on substrate 220. Hence, sublayer216 and epitaxial layer 217 have the same conductivity type.

[0072] A p-type collector region 270 is formed in epitaxial layer 217using the same processing steps as those used to form body region 228. Acollector contact region 272 is formed at top surface 238 withincollector region 270. Collector contact region is heavily doped toprovide a good ohmic contact for operating as a collector terminal ofIGBT 202.

[0073] A junction 271 is formed between epitaxial layer 217 andcollector region 270, both of which are relatively lightly doped andtherefore provide a low capacitance load to devices protected by TVSdevice 201. Gate terminal 213 is connected directly to lead 208 andcollector contact region 272 with interconnect line 241 as shown tooperate at the same potential as the collector terminal.

[0074] When IGBT 202 turns on in response to transient signal V_(TRANS),surge current I_(TRANS) flows from channel 230 laterally, i.e., in adirection parallel to top surface 238, along a current path 279 throughcollector region 270, collector contact region 272 and interconnect line241 to lead 208 as shown. Junction 271 forward biases to inject minoritycarriers into both epitaxial layer 217 and collector region 270, therebyconductivity modulating both regions and producing a low resistance paththat enhances the current capability of TVS device 201.

[0075] External connections are made through leads 208-209, both ofwhich are formed at top surface 238 and connected with standard wirebond or clip techniques.

[0076] In summary, several methods of providing a TVS device using MOSand IGBT structures are presented. The TVS devices exhibit superiorleakage current performance, while allowing for clamping voltages in thesub-5 volt range. Clamping voltages between 0.5 volts and 5 volts arereadily available through implantation control and high gain allowsrelatively constant clamping voltage characteristics.

What is claimed is:
 1. A method of using a transient voltage suppressiondevice, comprising: electrically coupling gate and drain terminals of ametal oxide semiconductor device; clamping a forward voltage appliedacross the transient voltage suppression device to be substantiallyequal to a threshold potential of the metal oxide semiconductor device;and clamping a reverse voltage applied across the transient voltagesuppression device to be substantially equal to a barrier potential ofthe metal oxide semiconductor device.
 2. The method of claim 1 whereinclamping the forward voltage comprises: applying a first potential of afirst polarity to the gate and drain terminals of the metal oxidesemiconductor device; and producing a first conductive state of themetal oxide semiconductor device with the first potential.
 3. The methodof claim 2 wherein clamping the reverse voltage comprises: applying asecond potential of a second polarity to the gate and drain terminals ofthe metal oxide semiconductor device; and producing a second conductivestate of the metal oxide semiconductor device with the second potential.4. A method of forming a transient voltage suppression device,comprising: electrically coupling gate and collector terminals of aninsulated gate bipolar transistor device; clamping a forward voltageapplied across the transient voltage suppression device to besubstantially equal to a threshold potential of the insulated gatebipolar transistor device; and clamping a reverse voltage applied acrossthe transient voltage suppression device to be substantially equal to abarrier potential of the insulated gate bipolar transistor device. 5.The method of claim 4 wherein clamping the forward voltage comprises:applying a first potential of a first polarity to the gate and collectorterminals of the insulated gate bipolar transistor device; and producinga first conductive state of the insulated gate bipolar transistor devicewith the first potential.
 6. The method of claim 5 wherein clamping thereverse voltage comprises: applying a second potential of a secondpolarity to the gate and collector terminals of the insulated gatebipolar transistor device; and producing a second conductive state ofthe insulated gate bipolar transistor device with the second potential.7. A method of using a transient voltage suppression device, comprising:electrically coupling gate and drain terminals of first and second metaloxide semiconductor devices; clamping a forward voltage applied acrossthe transient voltage suppression device to be substantially equal to afirst threshold potential of the first metal oxide semiconductor device;and clamping a reverse voltage applied across the transient voltagesuppression device to be substantially equal to a second thresholdpotential of the second metal oxide semiconductor device.
 8. The methodof claim 7 wherein clamping the forward voltage comprises: applying afirst potential of a first polarity to the gate and drain terminals ofthe first metal oxide semiconductor device; and producing a firstconductive state of the first metal oxide semiconductor device with thefirst potential.
 9. The method of claim 8 wherein clamping the reversevoltage comprises: applying a second potential of a second polarity tothe gate and drain terminals of the second metal oxide semiconductordevice; and producing a second conductive state of the second metaloxide semiconductor device with the second potential.
 10. A metal oxidesemiconductor device used as a transient voltage suppressor, thetransient voltage suppressor comprising: a semiconductor substratehaving first and second surfaces; a body region of a first conductivitytype formed in the first surface of the semiconductor substrate havingfirst and second surfaces; a drain region of a second conductivity typeformed in the second surface of the semiconductor substrate; and atrench gate region formed in the first surface of the semiconductorsubstrate.
 11. The metal oxide semiconductor device of claim 10 whereinthe transient voltage suppressor further comprises source regions of thesecond conductivity type formed in the first surface of the body region.12. The transient voltage suppressor of claim 10 wherein the trench gateregion extends from the first surface of the semiconductor substrateinto the drain region.
 13. The transient voltage suppressor of claim 12wherein the trench gate region comprises an insulative layer within thetrench gate region extending from the first surface of the semiconductorsubstrate to below the second surface of the body region.
 14. Thetransient voltage suppressor of claim 11 further comprising a sourcemetal layer on the first surface of the semiconductor substrateproviding an electrical contact to the first and second source regions.15. An insulated gate bipolar transistor device used as a transientvoltage suppressor, the transient voltage suppressor comprising: asemiconductor substrate having first and second surfaces; a body regionof a first conductivity type formed in the first surface of thesemiconductor substrate having first and second surfaces; a collectorregion of the first conductivity type formed in the second surface ofthe semiconductor substrate; and a trench gate region formed in thefirst surface of the semiconductor substrate.
 16. The insulated gatebipolar transistor device of claim 15 wherein the transient voltagesuppressor further comprises emitter regions of a second conductivitytype formed in the first surface of the body region.
 17. The transientvoltage suppressor of claim 15 wherein the trench gate region extendsfrom the first surface of the semiconductor substrate into the drainregion.
 18. The transient voltage suppressor of claim 15 wherein thetrench gate region comprises an insulative layer within the trench gateregion extending from the first surface of the semiconductor substrateto below the second surface of the body region.
 19. The transientvoltage suppressor of claim 16 further comprising a source metal layer(74)on the first surface of the semiconductor substrate providing anelectrical contact to the first and second emitter regions.
 20. Aprotection circuit, comprising: a utilization circuit (2)having an inputcoupled to receive an input signal at a first node; and a protectioncircuit coupled to the first node to substantially limit the inputsignal to a first level, the protection circuit including a transistorhaving a first conductor coupled to a control terminal of the transistorat the first node.
 21. The protection circuit of claim 20, wherein thetransistor includes a metal oxide semiconductor having a secondconductor coupled to a second node.
 22. The protection circuit of claim21 wherein the metal oxide semiconductor device comprises: asemiconductor substrate having first and second surfaces; a body regionof a first conductivity type in the first surface of the semiconductorsubstrate; source regions of a second conductivity type formed in thebody region; a gate electrode formed over the first surface of thesemiconductor substrate partially overlapping the source regions; adrain region of the second conductivity type formed in the secondsurface; and an electrical conductor coupling the gate electrode and thedrain region.
 23. The protection circuit of claim 21 wherein the metaloxide semiconductor device comprises: a semiconductor substrate havingfirst and second surfaces; a source region of a first conductivity typeformed in the first surface; a drain region of the first conductivitytype formed in the first surface; a gate electrode formed over the firstsurface of the semiconductor substrate partially overlapping the sourceand drain regions; and an electrical conductor coupling the gateelectrode and the drain region.
 24. The protection circuit of claim 23wherein the metal oxide semiconductor device further comprises: a firstregion of the second conductivity type formed in the second surface ofthe semiconductor substrate; and a second region of the secondconductivity type extending from the first surface of the semiconductorsubstrate into the first region.
 25. The protection circuit of claim 20,wherein the transistor includes an insulated gate bipolar transistorhaving a second conduction terminal coupled to a second node.
 26. Theprotection circuit of claim 25 wherein the insulated gate bipolartransistor comprises: a semiconductor substrate having first and secondsurfaces; a body region of a first conductivity type in the firstsurface of the semiconductor substrate; emitter regions of a secondconductivity type formed in the body region; a gate electrode formedover the first surface of the semiconductor substrate partiallyoverlapping the emitter regions; and a collector region of the firstconductivity type formed in the second surface.
 27. The protectioncircuit of claim 26 wherein the insulated gate bipolar transistorfurther comprises an electrical conductor coupling the gate electrodeand the collector region.
 28. The protection circuit of claim 26 whereinthe insulated gate bipolar transistor further comprises an electricalconductor coupling the gate electrode and the first surface of thesemiconductor substrate.
 29. A protection circuit, comprising: autilization circuit (2)having an input coupled to receive an inputsignal at first and second nodes; and a protection circuit (41)coupledto the first and second nodes to substantially limit the input signalbetween first and second levels, the protection circuit including, (a) afirst transistor having a first conductor coupled to the first node; and(b) a second transistor having a first conductor coupled to the secondnode.
 30. The protection circuit of claim 29, wherein the firsttransistor includes a metal oxide semiconductor having a secondconductor coupled to a control terminal of the first transistor.
 31. Theprotection circuit of claim 30, wherein the second transistor includes ametal oxide semiconductor having a second conductor coupled to a controlterminal of the second transistor and to the control terminal of thefirst transistor.